1. Field of the Invention
The present invention relates to semiconductor devices, and more specifically, it relates to a field-effect semiconductor device having a heterojunction structure, such as an HEMT structure or a DCHFET structure.
2. Description of the Related Art
Hitherto, as transistor devices operating in the microwave to millimeter wave range, field-effect transistors (hereinafter referred to as heterojunction FETs) having heterojunction structures have been used. In accordance with doping structures, the heterojunction FET is roughly classified into an HEMT (a high-electron-mobility transistor) using a modulation-doped structure and a DCHFET (a doped channel heterostructure FET) using a doped channel structure. In this connection, the latter DCHFET is also called a DMT, an MISFET, an HIGFET, and the like.
FIG. 1 is a schematic cross-sectional view showing a semiconductor structure of a conventional HEMT. In an HEMT 1, a buffer layer 3 is formed on a gallium arsenide (GaAs) substrate 2, a channel layer 4 composed of undoped indium gallium arsenide (InGaAs) is formed on the buffer layer 3, and a barrier structure 5 is formed on the channel layer 4. The barrier structure 5 in FIG. 1 comprises an n-type aluminum gallium arsenide (AlGaAs) layer 5a and an undoped AlGaAs layer 5b. The barrier structure 5 may comprises more than two layers, for example, an undoped AlGaAs layer, an n-type AlGaAs layer, and an undoped AlGaAs layer, or it may comprises only an n-type AlGaAs layer. On the barrier structure 5, in order to form good ohmic contacts with a source electrode 8 and a drain electrode 9, a contact layer 6 composed of n-type GaAs is formed. On the upper surface of the contact layer 6, the source electrode 8 and the drain electrode 9 are formed to be in ohmic contact with the contact layer 6 by heat treatment.
Between the source electrode 8 and the drain electrode 9, the contact layer 6 is etched so as to form a recess therein, and the undoped AlGaAs layer 5b in the barrier structure 5 is exposed in a recess 7. The recess is formed by selectively removing the contact layer 6 by etching using an etchant that does not etch AlGaAs but which etches GaAs, and by terminating the etching at the undoped AlGaAs layer 5b. A gate electrode 10 is formed on the upper surface of the undoped AlGaAs layer 5b that is exposed from the contact layer 6 in the recess 7 and is in Schottky contact with the undoped AlGaAs layer 5b. In addition, the surface of the HEMT 1 is covered with a protective layer 11 composed of SiN (silicon nitride).
In the HEMT structure described above, the energy-band structure (the bottom of the conduction band) under the source electrode 8 and the drain electrode 9 and the energy-band structure (the bottom of the conduction band) under the gate electrode 10 are as shown in FIGS. 2A and 2B, respectively. Electrons in the n-type AlGaAs layer 5a move over the heterojunction between the AlGaAs and the InGaAs to the channel layer 4 side that has a lower energy level. The electrons (two-dimensional electron gas) thus supplied from the barrier structure 5 to the highly purified channel layer 4 can drift without being scattered by donors in the barrier structure 5, so that the electrons have high mobility. That is, the channel layer 4 functions as a channel in which electrons flow, and the barrier structure 5 functions as a supplying source for supplying electrons to the channel layer, so that, when a potential difference is applied between the source electrode 8 and the drain electrode 9, a drain current flows in the channel layer 4.
FIG. 3 is a schematic cross-sectional view showing a semiconductor structure of a DMT among conventional DCHFETs. In a DMT 21, a buffer layer 23 is formed on a semi-insulating GaAs substrate 22, a channel layer 24 composed of n-type InGaAs is formed on the buffer layer 23, and a barrier structure 25 is formed on the channel layer 24. The barrier structure 25 in the DMT structure is formed of undoped AlGaAs. On the barrier structure 25, in order to form good ohmic contacts with a source electrode 28 and a drain electrode 29, a contact layer 26 composed of n-type GaAs is formed. The source electrode 28 and the drain electrode 29 are formed on the upper surface of the contact layer 26 and are in ohmic contact therewith by heat treatment.
Between the source electrode 28 and the drain electrode 29, the contact layer 26 is selectively etched so as to form a recess therein, and as a result, the barrier structure 25 is exposed in a recess 27. A gate electrode 30 is formed on the upper surface of the barrier structure 25 that is exposed from the contact layer 26 in the recess 27 and is in Schottky contact with the barrier structure 25. In addition, the surface of the DMT 21 is covered with a protective layer 31 composed of SiN.
In the DMT structure described above, the energy-band structure (the bottom of conduction band) under the source electrode 28 and the drain electrode 29 and the energy-band structure (the bottom of the conduction band) under the gate electrode 30 are as shown in FIGS. 4A and 4B, respectively. In the state in which voltage is not applied to the gate electrode 30, electrons are stored in the n-type channel layer 24, and when in this state a potential difference is applied between the source electrode 28 and the drain electrode 29, electrons as carriers move from the source electrode 28 to the drain electrode 29, so that a drain current flows.
In the HEMT structure and also in the DMT structure, one of the functions of the barrier structure is to form a barrier to the gate electrode. That is, due to the presence of a high energy barrier between the gate electrode and the channel layer (the case of the HEMT is shown in FIG. 2A, and the case of the DMT is shown in FIG. 4B), it is difficult for electrons to move over the barrier structure or tunnel through the barrier structure, so that current leakage to the gate electrode is prevented. Accordingly, the channel can be opened up to a higher current, and a higher breakdown voltage of the gate can be realized, so that high power output can be obtained.
The capacity of the barrier structure to inhibit current flow thus described is determined by the barrier height and the thickness of the barrier structure. The barrier height is determined by the difference between the work functions of the barrier structure and the gate electrode. In addition, the thickness of the barrier structure is determined by the dopant concentration therein. By forming a layer having lower dopant concentration as a barrier structure, the effective thickness of the barrier structure can be increased, and hence, by decreasing dopant concentration in the barrier structure, the capacity of the barrier structure to inhibit current flow to the gate electrode can be significantly increased.
However, on the other hand, since the barrier structure is used as a passage for allowing current to flow between the channel layer and the drain electrode or the source electrode, the barrier structure offers a considerable resistance to the flow of drain current. Accordingly, in order to reduce series resistance between the source and the drain, the dopant concentration in the barrier structure must be increased so as to decrease the resistance.
Consequently, in order to increase the capacity of the barrier structure to inhibit current flow, the dopant concentration of the barrier structure must be decreased; however, as a result, the barrier structure has a higher resistance and the series resistance between the source and the drain is increased. In contrast, in order to reduce the series resistance between the source and the drain, the dopant concentration of the barrier structure must be increased so as to have a lower resistance; however, as a result, the capacity of the barrier structure to inhibit current flow is decreased, so that current leakage to the gate electrode is increased.
Because of the technical trade-off described above, even though a heterojunction FET structure having a lower series resistance in addition to having a higher barrier function has been pursued, the FET mentioned above has been heretofore difficult to produce.
In addition, in the conventional structure, when the contact layer is selectively etched so as to form a recess therein, the contact layer is also etched in the lateral direction, and hence, flat zones (over-etched portions) are formed at both sides of the gate electrode. In the case of the DMT, as shown in FIG. 5, since depletion layers 33 extend downward from flat zones 32, the series resistance between the source electrode 28 and the drain electrode 29 is further increased, and hence, DC characteristics of the device are further degraded.
In order to solve the technical problems described above, an object of the present invention is to provide a field-effect semiconductor device provided with a barrier structure having low series resistance to the source and the drain electrode in addition to functioning as a high barrier to the gate electrode.
The field-effect semiconductor device comprises: a channel layer; a barrier structure formed on the channel layer and comprising a plurality of semiconductor layers; a plurality of ohmic electrodes formed above the barrier structure; and a Schottky electrode formed on the barrier structure between the ohmic electrodes. The barrier structure has an electron-affinity less than that of the channel layer and comprises at least two heavily doped layers and a lightly doped layer provided therebetween. The barrier structure may comprise an n-type layer, an undoped layer, and an n-type layer, stacked in that order. The bottom of the Schottky electrode may be in contact with the lightly doped layer in the barrier structure, and the lightly doped layer is preferably 2.5 to 10 nm thick. The semiconductor layers forming the barrier structure may be composed of AlGaAs, and the channel layer may be a heavily doped semiconductor layer.
As described above, according to the present invention, since the field-effect semiconductor device having lower series resistance can be realized while a high Schottky barrier effect is maintained, a field-effect semiconductor device can be realized, which has FET characteristics, such as, high breakdown voltage, maximum drain current, high Gm, and low on-resistance.
For the purpose of illustrating the invention, there is shown in the drawings several forms which are presently preferred, it being understood, however, that the invention is not limited to the precise arrangements and instrumentalities shown.